1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of depositing a titanium nitride layer using a two-step deposition process, which can improve step coverage of an upper capacitor electrode of a capacitor while simultaneously improving resistance distribution of a node resistor.
2. Description of the Related Art
FIG. 1 illustrates a cross-sectional view of a conventional dynamic random access memory (DRAM) device. A semiconductor substrate 100 includes a cell region 110 and a peripheral region 115.
A MOS transistor is formed on an active region of the cell region defined by a device isolation film 121. The MOS transistor includes a gate oxide layer 123, a gate electrode 124 and doped regions 126 for source and drain electrodes.
A bit line 128 is connected to one of the doped regions 126 via a contact 134. A capacitor is formed on an insulating layer 130. The capacitor includes a lower capacitor electrode 140, which is a storage node connected to a doped region 126, which is not in contact with a bit line 128, via a contact 132, a dielectric layer 150 and an upper capacitor electrode 161. A node resistor 163 is formed on a portion of the insulating layer 130 over the peripheral region 115.
In order to form the upper capacitor electrode 161 and the node resistor 163, a titanium nitride layer 160 is deposited using an atomic layer deposition. In this case, the upper capacitor electrode 161 and the node resistor 163 require different deposition conditions.
In other words, the titanium nitride layer used as the upper capacitor electrode 161 is required to have excellent step coverage in order to obtain excellent electrical characteristics with respect to leakage current, capacitance and a high time dependent dielectric breakdown (TDDB). However, the titanium nitride layer used as the node resistor 163 is required to have uniformity that is optimized for a resultant device. In order to obtain optimized uniformity, the titanium nitride layer should have an optimized resistance distribution. An optimized resistance distribution is preferable because when a resistance distribution of the node resistor 163 is large, a possibility of deviating from a range of desired resistance values is increased. Deviation from the range of desired resistance values results in abnormal operation, thereby lowering manufacturing yield.
However, since a deposition condition of the titanium nitride layer for obtaining excellent step coverage conflicts with a deposition condition of the titanium nitride layer for obtaining an optimized resistance distribution, a conventional method of depositing the titanium nitride layer using atomic layer deposition cannot satisfy the two deposition conditions simultaneously.
In order to obtain excellent step coverage, the titanium nitride layer should be deposited in a condition wherein a ratio of NH3 to TiCl4 is low, whereas, to improve the resistance distribution, the titanium nitride layer should be deposited in a condition wherein a ratio of NH3 to TiCl4 is high.
FIG. 2 is a photograph illustrating step coverage of a titanium nitride layer deposited by conventional atomic layer deposition. An upper photograph of FIG. 2 illustrates step coverage of a portion of the titanium nitride layer corresponding to an upper portion of the capacitor. A lower photograph of FIG. 2 illustrates step coverage of a portion of the titanium nitride layer corresponding to a lower portion of the capacitor.
Referring to FIG. 2, when a ratio of NH3 to TiCl4 is 16.7, the portion of the titanium nitride layer corresponding to the upper portion of the capacitor is deposited to a thickness of 150 xc3x85, while the portion of the titanium nitride layer corresponding to the lower portion of the capacitor is deposited to a thickness of 30 xc3x85. That is, it may be understood that the step coverage is inferior when a ratio of NH3 to TiCl4 is high.
FIGS. 3 and 4 are photographs illustrating resistance distribution and deposition thickness of a titanium nitride layer deposited using conventional atomic layer deposition.
When the titanium nitride layer is deposited on a patterned wafer by conventional atomic layer deposition, thickness of the titanium nitride layer varies at different locations of the wafer. This variance occurs because there exists a loading effect that is dependent upon pattern density. Since the pattern density varies at different locations of the wafer, the loading effect also varies, and the thickness of the titanium nitride layer deposited on the patterned wafer is not uniform.
For example, a titanium nitride layer may be deposited on a bare, unpatterned wafer to a uniform thickness of 320 xc3x85. If a titanium nitride layer is deposited under the same deposition conditions on a patterned wafer, however, a thickness of a portion of the titanium nitride layer corresponding to a central portion of the patterned wafer is 160 xc3x85, whereas a thickness of a portion of the titanium nitride layer corresponding to an edge portion of the patterned wafer is 195 xc3x85, as shown in FIG. 4. In this case, the portion of the titanium nitride layer corresponding to the central portion of the wafer has a resistance value of 3239 xcexa9, whereas the portion of the titanium nitride layer corresponding to the edge portion of the wafer has a resistance value of 2986 xcexa9. Consequently, the resistance distribution of the titanium nitride layer formed on the patterned wafer is not uniform.
Referring to FIG. 4, it may be understood that since a central portion and an edge portion of the wafer differ in loading effects, the portion of the titanium nitride layer formed on the central portion of the wafer is thinner than the portion of the titanium nitride layer formed on the edge portion of the wafer.
Table 1 shows a loading effect and a thickness of a titanium nitride layer according to a location on a bare, unpatterned wafer and a patterned wafer.
In Table 1, xe2x80x9cA-thicknessxe2x80x9d denotes a thickness of a titanium nitride layer formed on a bare wafer, and xe2x80x9cB-thicknessxe2x80x9d denotes a thickness of a titanium nitride layer formed on a patterned wafer. Here, the titanium nitride layers are deposited under identical conditions.
As set forth in Table 1, the titanium nitride layer formed on the bare wafer has a uniform thickness regardless of a location on the wafer, while the titanium nitride layer formed on the patterned wafer has a non-uniform thickness. Specifically, a portion of the titanium nitride layer formed on the central portion of the wafer is thinner than a portion of the titanium nitride layer formed on the edge portion of the wafer. As a result, since the thickness of the titanium nitride layer varies depending on location on the wafer, the resistance distribution of the node resistor is non-uniform.
In an effort to overcome the problems described above, it is a feature of an embodiment of the present invention to provide a method of forming a titanium nitride layer which can improve step coverage of an upper capacitor electrode while simultaneously improving resistance distribution of a node resistor.
In order to provide this feature, a preferred embodiment of the present invention provides a method of manufacturing a semiconductor device having an upper capacitor electrode and a node resistor, including depositing a thin film at a first deposition rate on an edge portion of a wafer and at a second deposition rate on a central portion of a wafer to form the upper capacitor electrode and the node resistor. Preferably, the thin film is a titanium nitride layer.
Preferably, a portion of the thin film corresponding to the central portion of the wafer is deposited to a thickness greater than a thickness of a portion of the thin film corresponding to the edge portion of the wafer.
The non-uniform deposition thickness may be achieved by depositing the thin film in multiple layers and under variable deposition conditions. Specifically, depositing the thin film may include depositing a first thin film at a constant deposition rate on both the edge portion and the central portion of the wafer, and depositing a second thin film at a deposition rate to the edge portion of the wafer that is smaller than a deposition rate to the central portion of the wafer. Also, the second thin film may be deposited at a higher deposition pressure than the first thin film.
Preferably, the first thin film is deposited under a deposition condition wherein a ratio of NH3 to TiCl4 is relatively low, e.g., less than about 3.3, and the second thin film is deposited under a deposition condition wherein a ratio of NH3 to TiCl4 is relatively high, e.g., greater than about 16.7. In addition, a distance for a deposition gas to reach a central portion of the wafer may be longer than a distance for the deposition gas to reach an edge portion of the wafer.
The first thin film may be deposited to a thickness that is between about 50% to 90% of a total thickness of the thin film, and the second thin film may be deposited to a thickness that is between about 10% to 50% of the total thickness of the thin film.
The thin film may be deposited by atomic layer deposition or chemical vapor deposition.
According to another embodiment of the present invention, a method of manufacturing a semiconductor device is provided, including depositing a first titanium nitride layer under a deposition condition that promotes excellent step coverage and depositing a second titanium nitride layer under a deposition condition that promotes uniform resistance distribution.